Understanding 100G OTN


OTN uses a similar multi-lane mechanism to 100G Ethernet to achieve 100G rates.

The parallel interfaces are defined in an appendix of the G.709 recommendation.  The recommendation includes definitions of parallel interfaces for both 40G and 100G rates and within this a new signal was defined for parallel interfaces – the Optical Channel Transport Lane (OTL).

At the 100G rate the OTN interface defined is the OTU4 with a nominal bit rate of 112Gb/s, as a client interface OTU4 is presented as a parallel client  with the OTU4 mapped into  an OTL4.n.

An OTL4.n  is a 100G interface where n identifies the number of parallel lanes in use. For example OTL 4.4 denotes an OTU4 mapped over 4 optical lanes while OTL 4.10 denotes an OTU4 mapped over 10 optical lanes.

OTN frames are serialised into a stream of blocks that are then distributed over 20 logical lanes

The method used for OTN parallel transmission is similar to that used for 100G Ethernet. The basic OTN frame structure remains unchanged and frames are serialised into a stream of blocks. These blocks are then distributed in a round-robin manner over 20 logical lanes – similar to the PCS lanes used for 100G Ethernet. Logical lanes are multiplexed into 10Gb/s lanes for the physical interface to the CFP in a similar manner to the PCS lane to CAUI lane multiplexing used in 100G Ethernet.

One key difference between the OTN and Ethernet multi-lane implementations is that OTN does not then add markers to the logical lanes to identify the lanes.

Instead of using lane markers within the logical lanes the Logical Lane Marker (LLM) is used to identify the lanes. Within the OTN frame there are 6 bytes reserved for framing purposes (A1 & A2 bytes) however only 32 bits of these are used for framing purposes leaving the 2nd and 3rd A2 bytes without function.

Only 32 bits of the A1 & A2 bytes are used for framing so the last A2 byte is now used as the Logical Lane Marker

The 3rd A2 byte has now been allocated as the LLM.

The LLM has two separate functions – logical lane identification and also skew handling. The LLM value is utilised in a slightly different manner for each function. The LLM cycles in a loop from 0 to 239 with each OTN frame incrementing the byte value.

For logical lane recovery the multi-lane mechanism only requires the identification of the 20 logical lanes. On the receiving end of the link the element will perform a modulus 20 operation on the LLM. In this case the LLM is converted into a running counter from 0-19 instead of 0-239.

For skew tolerance the total LLM value is used. As this is cycling across 240 values it is possible to identify individual frames and tolerate skew of up to 119 frame periods – for OTU 4 this is 139 μs. If we compare Ethernet and OTN skew tolerance OTN is far more tolerant of this condition. Ethernet specifies a minimum skew tolerance of 928 bits, however with OTU4 the tolerance is up to 119 frames – 485520 bytes.

By utilising a single fixed byte to identify the logical lane assignment it was necessary to take another step in order for each lane to be identified. As the LLM is in a fixed location by simply transmitting the signal over the multi-lane interface the LLM would only ever appear in a single lane and therefore identify only a single lane.  Instead OTN uses a logical lane rotation method so that each successive OTN frame uses a different logical lane as the first lane. In this way the LLM will eventually be distributed over every logical lane.

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