100G Ethernet includes a process that continually monitors the performance of received PCS data and triggers an alarm condition in the event that an excessive error ratio is detected.
When receiving data at the PCS each lane is checked for errors in the 2 bit sync header in each 66b block. A counter is maintained for the total number of errors in the sync headers received across all 20 PCS lanes.
If the number of errors within a 500ms window exceeds 97 then the High BER condition is set.
The root cause of the High BER condition may be investigated by observing how many PCS lanes are showing sync header errors and how these are mapped to the CAUI. Troubleshooting links and understanding how PCS & CAUI conditions can pinpoint the source of an alarm such as High BER will be covered in a future post.