Understanding the condition of the PCS lanes is crucial to troubleshooting 100G links during network deployments. At the most basic level understanding that there are errors at the PCS indicates that the root cause of the fault lies with the physical signalling and not at the MAC layer or any of the high network layers […]
100G Ethernet includes a process that continually monitors the performance of received PCS data and triggers an alarm condition in the event that an excessive error ratio is detected. When receiving data at the PCS each lane is checked for errors in the 2 bit sync header in each 66b block. A counter is maintained […]
Now more than ever latency is a key network quality metric, with financial institutions and other Enterprise customers demanding absolutely minimal latency from their service provider. With Skew being an inherent part of a 100G Ethernet link, field engineers starting to roll out these services commonly ask how will Skew levels affect the latency measurements […]
The alignment marker is used for the identification of the PCS lanes. They allow the receiving network equipment to identify the lanes as they are received so that that they can be re-ordered. So what is an alignment marker? An alignment marker is a single 66 bit block that is inserted into the stream of […]
On the 100G Ethernet interface the Loss Of Block Lock (LOBL) alarm is raised when it is not possible to lock onto the sync. header within the 64b/66b line coded blocks. As the serial stream of blocks are distributed over the 20 PCS lanes during transmission the LOBL alarm should be reported within a specific […]
The multi-lane architecture within 100G Ethernet that comprises the PCS Lanes, CAUI and Gearbox (depending on CFP) represent a whole new sublayer of the network that must be specifically tested. This new sublayer exists only between two directly adjacent network elements that are connected via the CFP interfaces. To support this there are a number […]
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