Alignment Markers And Associated Alarm & Error Conditions


The alignment marker is used for the identification of the PCS lanes. They allow the receiving network equipment to identify the lanes as they are received so that that they can be re-ordered.

So what is an alignment marker?

An alignment marker is a single 66 bit block that is inserted into the stream of blocks in each PCS lane. It is not passed through the line coding mechanism itself and so the markers themselves are formatted specifically to be DC balanced.

Format of the PCS lane alignment marker

The first two bits of the alignment marker are fixed in order to provide a framing function for the marker.

The M bytes contain specific values that are defined in 802.3ba to identify each lane from 0 through 19.

The Bit Interleaved Parity (BIP) contain a parity check calculated over the bits from the previously inserted alignment marker and all the subsequently transmitted blocks up to the current marker. The second BIP field contains a bit inversion of the original BIP in order to maintain line balancing.

The markers are inserted into the PCS lanes at regular intervals, with 16383 66b blocks of data being inserted between each marker, the BIP is calculated across all 16383 blocks and the preceding alignment marker block.

At the receiving end of the link the device will initially need to lock onto the stream of blocks being received from each PCS lane. One this lock onto the sync headers of the blocks is achieved the alignment markers can be detected. At that point the receiving device will be able to re-order the blocks into the correct sequence. During this process the alignment marker blocks are removed before the blocks are serialised.

Obviously the alignment marker is a critical part of the parallel signal generation, and so there are various error & alarm conditions that will need to be measured during testing:

  • The Invalid Marker error should be counted whenever a tester device detects an alignment marker is that does not contain valid lane identification bytes.
  • The test device should also calculate the BIP for received blocks in a lane and compare this result to the BIP value stored within the marker. In the case where the calculated BIP does not match the received BIP value within the alignment marker a BIP error should be counted.
  • In the case that 97 consecutive BIP errors are measured on an individual PCS lane the Hi-BER alarm should be counted against that lane.
  • Finally if the situation arises where a valid alignment marker are not received for 4 consecutive alignment markers the Loss Of Alignment Marker (LOAML) alarm should be measured for that PCS Lane.

Overall if any of these error or alarm conditions are detected on any PCS lanes this will constitute a very serious defect in the link and would require immediate troubleshooting to identify the component – either the line card, CFP transceiver or connecting fibre – that is causing the problem.

2 Responses to "Alignment Markers And Associated Alarm & Error Conditions"
  1. Not sure, but I don’t think that the parity is checked unless there is Alignment Lock. Alignment Lock can’t be achieved with only the first AM – it needs to receive subsequent alignment markers as well – so the first BIP would be ignored in that case.

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